# Synology DS109

interface ftdi
ftdi_vid_pid 0x0403 0x6010

ftdi_layout_init 0x0008 0x000b
ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010
ftdi_layout_signal nSRST -data 0x0040 -oe 0x0040

adapter_khz 2000

# length of reset signal: [ms]
adapter_nsrst_assert_width 1000

# don't talk to JTAG after reset for: [ms]
adapter_nsrst_delay 200

source [find target/feroceon.cfg]

reset_config trst_and_srst srst_nogate

proc ds109_init { } {

	# We need to assert DBGRQ while holding nSRST down.
	# However DBGACK will be set only when nSRST is released.
	# Furthermore, the JTAG interface doesn't respond at all when
	# the CPU is in the WFI (wait for interrupts) state, so it is
	# possible that initial tap examination failed.  So let's
	# re-examine the target again here when nSRST is asserted which
	# should then succeed.
	jtag_reset 0 1
	feroceon.cpu arp_examine
	halt 0
	jtag_reset 0 0
	wait_halt
	#reset run
	#soft_reset_halt

	arm mcr 15 0 0 1 0 0x00052078

	mww 0xD00100e0 0x1b1b1b9b ;#
	mww 0xD0020134 0xbbbbbbbb ;#
	mww 0xD0020138 0x00bbbbbb ;#
	mww 0xD0001400 0x43000C30 ;#  DDR SDRAM Configuration Register
	mww 0xD0001404 0x39743000 ;#  Dunit Control Low Register
	mww 0xD0001408 0x22125551 ;#  DDR SDRAM Timing (Low) Register
	mww 0xD000140C 0x00000833 ;#  DDR SDRAM Timing (High) Register
	mww 0xD0001410 0x0000000d ;#  DDR SDRAM Address Control Register
	mww 0xD0001414 0x00000000 ;#  DDR SDRAM Open Pages Control Register
	mww 0xD0001418 0x00000000 ;#  DDR SDRAM Operation Register
	mww 0xD000141C 0x00000C62 ;#  DDR SDRAM Mode Register
	mww 0xD0001420 0x00000042 ;#  DDR SDRAM Extended Mode Register
	mww 0xD0001424 0x0000F1FF ;#  Dunit Control High Register
	mww 0xD0001428 0x00085520 ;#  Dunit Control High Register
	mww 0xD000147c 0x00008552 ;#  Dunit Control High Register
	mww 0xD0001500 0x00000000 ;#
	mww 0xD0001504 0x07FFFFF1 ;#  CS0n Size Register
	mww 0xD0001508 0x10000000 ;#  CS1n Base Register
	mww 0xD000150C 0x00000000 ;#  CS1n Size Register
	mww 0xD0001510 0x20000000 ;#
	mww 0xD0001514 0x00000000 ;#  CS2n Size Register
	mww 0xD000151C 0x00000000 ;#  CS3n Size Register
	mww 0xD0001494 0x003C0000 ;#  DDR2 SDRAM ODT Control (Low) Register
	mww 0xD0001498 0x00000000 ;#  DDR2 SDRAM ODT Control (High) REgister
	mww 0xD000149C 0x0000F80F ;#  DDR2 Dunit ODT Control Register
	mww 0xD0001480 0x00000001 ;#  DDR SDRAM Initialization Control Register
	mww 0xD0020204 0x00000000 ;#  Main IRQ Interrupt Mask Register
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "
	mww 0xD0020204 0x00000000 ;#              "

	mww 0xD0010000 0x01111111 ;#  MPP  0 to 7
	mww 0xD0010004 0x11113322 ;#  MPP  8 to 15
	mww 0xD0010008 0x00001111 ;#  MPP 16 to 23
}

proc ds109_load { } {
	# load u-Boot into RAM and execute it
	ds109_init
	load_image u-boot.bin 0x00600000 bin
	resume 0x00600000
}
